Integrated Circuit (“IC”) design involves several phases including at least one testing phase. The tests used to check the design features are generated during a Design for Test (“DFT”) phase. The DFT features are also integrated directly onto the IC. Using DFT techniques, a designer can comprehensively test the manufactured IC for quality and coverage. Typically, the testability features included on the IC facilitate manufacturing tests to ensure that the components of the IC behave in a manner consistent with the expected component behavior.
Different IC standards of reliability are demanded across industries. Many different industries rely on technical inventions that include IC design with a memory component. Some of these industries require that these memory component ICs meet their zero-defect policy for faults in on-board memory components. For example, automotive and health industries require that ICs used in their products are produced using a high silicon quality and that the ICs are produced reliably without manufacturing faults. Memory components used in the automobile industry must be subjected to strict tests and pass without failure due to the inherent risk to human safety when an IC and/or its associated memory component has a fault or fails. Similarly, memory components used in the medical devices industry must also be subjected to strict tests and pass without failure due to their usage in protecting, monitoring, and correcting human health issues. In these industries, an uncorrected fault or failure could contribute to an accident or loss of human life. Faults of an IC and its associated memory component in medical devices and automobiles, therefore, are subject to strict testing regulations.
The Joint Test Action Group (“JTAG”) Institute of Electrical and Electronics Engineers (“IEEE”) Standard 1149.1, which is sometimes referred to as the IEEE Standard Test Access Port and Boundary-Scan Architecture, was adopted in 1990 to address the industry-wide need for standardized on-board test input pins. Using the input pins, the circuit, but not specifically the memory, can be tested and the output from the circuit can be diagnosed and/or repaired during the component's normal functional operation. To do so, the IEEE 1149.1 standard mandates the existence of a 16-state state machine, called a JTAG macro, and four (or optionally five) Test Access Ports (“TAP”) to be present in designs. The five TAP pins include: (1) test instructions, (2) control pin one, (3) control pin two (optional), (4) serial test data input, and (5) serial test data output. Implementation of the JTAG IEEE 1149.1 is often integrated into an IC using the serial IEEE 1149.1 test bus and associated ASSET software.
As described above, IC design generally includes at least one on-chip memory device. Such a memory device could be volatile or non-volatile, and could include at least any of: Random-Access Memory (“RAM”) such as Dynamic Random-Access Memory (“DRAM”) or Static Random-Access Memory (“SRAM”); Read-Only Memory (“ROM”) such as an Electronically Erasable Programmable Read-Only Memory (“EEPROM”); flash memory; solid-state storage; magnetic tape; hard disk drives; and optical drives. Moreover, industry demand has resulted in a steady increase in product memory density. To provide the demanded memory increase needed on board the ICs being developed, memory is now often integrated as embedded memory within digital signal processors (DSPs), application-specific integrated circuits (ASICs), and microprocessors. Testing of memory devices and/or memory boards is increasingly complicated and requires substantial time and resources.
Memory testing can be performed in one of two phases: during a pre-manufacturing design phase or on board the IC. As described below, before manufacturing, the IC design (not the physical memory) including a correction logic design, which is called Error Correction Code (“ECC”) logic, is subjected to software testing and simulation. The software testing and/or simulation occurs when the design is modeled entirely using a programming language, such as Verilog or Very High Speed Integrated Circuit (“VHSIC”) Hardware Description Language (“VHDL”), to describe the digital and mixed-signal systems. After the design phase the IC is manufactured and placed into, and on-board the IC, the physical memory (not the design, and not the ECC) is subjected to hardware testing.
In circumstances in which the memory components are subject to a zero-defect policy, Error Correction Code (“ECC”) logic also is included on board the IC and applied to the memory components. The ECC logic is used to diagnose and then correct any data output from the memory that is diagnosed as faulty. The ECC logic can correct data output up to a predetermined number of faulty data bits of the memory. As mentioned in the foregoing, ECC logic is only tested using functional patterns while the IC is in a design-phase. The actual output from the physical memory is not tested using the ECC logic after the IC is manufactured. ECC logic is not tested, using functional patterns, after the manufacture of the IC because of the large number of test patterns (2n) that would need to be applied to the input pins (n-inputs) of an IC using Automatic Test Pattern Generation (“ATPG”). ATPG is an electronic design automation method that is used to generate scan data that, when applied to the IC, enables the Automated Test Equipment (“ATE”) to distinguish between the expected output data and the returned output data from the Design Under Test (“DUT”). Using the limited test pin budget available from the ATE during the ATPG, on-chip testing of the ECC logic could take years. In addition, on-chip testing of the ECC logic would not make sense because during ATPG the values stored in the memory are unknown, and therefore the values output by the ECC logic would be incomprehensible and have no value to the observer.
At the point in time when the memory is prepared, manufactured, and/or loaded onto the IC, the physical memory and its ability to hold supplied values at specified addresses is directly tested. Memory testing is completed on-board the IC using Memory Built-In Self-Test (“MBIST”) hardware. The MBIST is capable of generating a series of read operations and a series of write operations, which are also known as algorithms, to load bits to and then subsequently unload the bits from the memory. A record of the loaded bits are compared to the bits unloaded from the memory for purposes of completing the MBIST test. Physical memories are only tested using the MBIST logic on-board the IC. Physical memory is not tested before the manufacture of the IC because the ability of a software modeled register to hold a value at a specific point in software memory is not representative of the ability of an actual hardware physical memory component to function properly.
The complexity of highly reliable chips demanded by the market continues to increase. In order to service the demands for these highly reliable chips, which are to be implemented in high-risk technologies, the results from the ECC tests and the physical memory tests must both be reliable. However, as the demands for these chips increase, the serialized testing of the ECC logic in design-mode and then the on-board testing of the physical memory with an MBIST is insufficient. The serial testing, the assumptions inherent to the serial testing, and the failure to address chip aging, among other concerns, obstruct the designer's ability to promise a completely reliable IC.
The currently available testing scheme, in which: (i) the ECC logic is not tested on-board the chip, and (ii) the ECC logic is tested only with a software design of a memory and not an actual physical memory as well as the other on-board IC connections, has not provided the most accurate and reliable test results. In addition, the current testing scheme for the memory components only checks the reliability of the ECC logic in a design phase. Failure to check the reliability of the ECC logic on-board the IC, particularly when the ICs are expected to have a long life span, can no longer be accepted in the high-risk industries. Moreover, modifications to the ICs are always expected to utilize a very small number of additional on-board components including gates and/or combinatorial logic. IC designers, with reliability concerns in mind, must still minimize the added logic for testing in order to meet customer demands for small chip size and minimize the cost per chip increase passed on to the consumer.